1. Technical Field
The present invention relates generally to a phase change random access memory device, and more particularly, to a phase change random access memory device including sense amplifier groups.
2. Related Art
In general, the data processing speeds of the nonvolatile memories such as the magnetic memory or the phase change random access memory (PCRAM) that retain data even when power is cut off are comparable to the data processing speeds of the volatile random access memory (RAM).
FIG. 1 is a circuit diagram of a conventional phase change random access memory device.
Referring to FIG. 1, the conventional phase change random access memory device 50 includes a plurality of sense amplifier groups 10, 20, and 30.
The plurality of sense amplifier groups 10, 20, and 30 typically correspond one-to-one to the first to third sense amplifier drivers 12, 22, and 32, respectively. When an external sense amplifier enable signal en is enabled to notice an operation time of sense amplifiers, the corresponding sense amplifier driver 12, 22, or 32 of the selected cell block is driven.
The first sense amplifier group 10 includes a first coupling prevention unit 14 and a first input unit 16. The first coupling prevention unit 14 is configured to prevent a first input signal in0 applied from outside from being distorted by coupling. The first input unit 16 is configured to output the first input signal in0 applied from an input voltage terminal to the first sense amplifier driver 12, in response to the level of the enable signal en.
The second and third sense amplifier groups 20 and 30 also include second and third coupling prevention units 24 and 34, respectively, and second and third input units 26 and 36, respectively. The second and third sense amplifier groups 20 and 30 are configured in the same manner as the first sense amplifier group 10 as described above.
The first coupling prevention unit 14 includes, for example, a MOS capacitor T1. The gate of the MOS capacitor T1 is electrically coupled to an enable signal line 44, and a source/drain of the MOS capacitor T1 is coupled to an input signal line 42.
As such, the MOS capacitors T1, T2, and T3 of the respective coupling prevention units 14, 24, and 34 are electrically coupled to the input signal line 42 and individually receive different voltage signals from each other.
FIGS. 2 and 3 illustrate the layout structure of the first to third coupling prevention units 14, 24, and 34 of the conventional phase change random access memory device. Referring to FIGS. 2 and 3, impurities are implanted into the regions of a semiconductor substrate 55, on which the first to third coupling prevention units 14, 24, and 34 are to be formed, thereby forming a plurality of active regions 54a, 54b, and 54c. 
In this case, however, a barrier rib (not illustrated) should be formed between the respective active regions 54a, 54b, and 54c, or the first to third coupling prevention units 14, 24, and 34 should be spaced at even intervals P1 and P2 from each other, in order to discriminate the active regions from each other. Therefore, there is a limit in reducing the entire size of the phase change random access memory device.